More Requirements on Verification / QA / Design / CAD etc. Please let us know if you have any candidates that fits into the following JDs :

Location : Hyderabad, India

Start Date : ASAP


QA SMTS /MTS

Summary : Candidate should have 12 to 15 years of strong technical experience in Microsoft .Net technologies, C++, Install. He should have hands on architect, design & development level experience for more than 10 years. Should be innovative and work in the environment of lot of unknowns independently. Good communication & presentation skills. Should be committed and fits in our environment.

Please find the JD and Responsibilities for SMTS/PMTS

Job Description for SMTS/PMTS

· Should have 10 to 15 yrs of experience in software development

· Should have at least 8 to 10 yrs of experience in C, C++, .NET, C#, Win Forms, WPF

· Should have excellent skills in designing and Architecting windows based applications

· Should have excellent knowledge on UML, Design Patterns, architectural patterns, enterprise application patterns

· Should have worked as architect for at least two end to end projects

· Should have worked in projects which involves teams from multiple geographies

· Should have worked in projects which uses .NET as front end and C or C++ code as middle ware

· Experience in driver development environment is added advantage

· Experience in Graphics domain is added advantage

Responsibilities:

· The ideal candidate is responsible for the design of the entire application

· Should review the design done by the junior team members

· Should review the code written by the junior team members

· Mentor the team on design activities

· Participate in technical discussion with other teams sitting in other geographies



Sr. Quality Engineer



Automation Test Engineer – Graphics

Key Responsibilities:
· Develop test cases / test plans consisting of functional testing, negative testing, customer / end user testing, stress, performance, reliability and usability testing

· Modify / create test cases and build the test plan, determine Hardware and ASIC coverage and assist with test case optimization / efficiency (with guidance from the onsite team)

· Develop test scripts and deploy in AMD’s Test Automation System (TACC)

· Maintain TACC

· Manage system (PC) configuration, Windows and Linux OSs

· Train / educate local staff on new features/requirements and or tools

· System / Environment maintenance – this may involve building new 3D Captures / Game cache

· Participate in all phases of the software development cycle including but not limited to development of test strategies/methodology/quality

· Test Execution, Problem triaging, prioritizing and status reporting



Qualification, Skills and Experience Requirement:
o Essential

· First class BE / BTech with Computer Science / Electronics

· Strong knowledge of or interest in 3D graphics concepts, DirectX and / or OpenGL, middleware, and game engine technologies

· Total 3-5 years of experience in multi-disciplinary QA process environments.

· Min. 2 years of experience in Test automation.

· Exp. in testing embedded solutions

· Exposure to benchmarking of product performance.

· Strong in Perl, Shell and Windows scripting

· Familiar with aspects of product development, such as lifecycles, software process, test methodology and product deployment

· Test case / plan execution and generation

· Self-starter with an ability to achieve successful outcomes in a non-hierarchical environment

· Detailed oriented, ability to multitask through planning / organizing.

· Communication skills - excellent oral, written and presentation skills

· Interest in 3D games and the game development process

· Knowledge of PC and Graphics Technologies

· Strong analysis, problem solving and reporting skills.

o Desired

· Knowledge of database and reporting tools such as Crystal report, Cold Fusion.

· Strong in C, C++, Linux, .Net





PSE





SOC verification Lead



MTS



8-12 yrs experience for SOC verification Lead.

· Must have worked on atleast 1-2 Complex SOC Tape-outs

· Must have designed/verified the SOC level tests (functiona/DFT)

· Must have good understanding of DFT/DFD and SOC verification

o Exposure to all aspects of DFT verification including Jtag/MBist/LBist/scan/DebugBus etc

· Processor design/verification experience is a bonus

The job will require the person to act as a lead for a team of 4-8 engineers. Lead level experience is desirable. He should have good communication skills to interact with the counterparts across the world.

SDE
5-8 yrs experience in ASIC/SOC design and verification

Exposure to processor verification is highly preferred

Must have taped-out at least one successful SOC

Appropriate candidate will have the skills of:
• Verilog/High level verification
• SOC verification and random test generation
• Testplanning & test writing especially for processor verification
• Exposure to tools like: VCS/NCSim, Debussy
• Perl and scripting
• Knowledge/exposure to complete SOC tape-out flow



SDE / MTS





Sr. Design Engineer
(Experience: 4-6yrs)

Candidate should posses good mix of front end skills with a good working experience on power estimation and low power design techniques.
• Sound knowledge of low power methodology and power estimation procedures
• Working experience with power estimation tools (Power Theater/PT-PX) and CLP flow
• Hands on experience with Low power methodologies using UPF/CPF
• Needs to have sound fundamentals in RTL design and micro architecture
• Needs hands on experience with LEC/Lint/CDC
• Good understanding on Synthesis/STA flows
• Good Perl/TCL scripting skills
• Experience working with global teams



SDE / MTS





· >5 years experience in ASIC/SOC design and verification

Exposure to processor architecture and verification is highly preferred
Must have taped-out at least one successful SOC
Appropriate candidate will have the skills of:



· Verilog/System Verilog/x86/C++ based High level verification
SOC functional verification strategy development and execution

· Strong skills and motivation in complex Architecture Debug

· Exposure to verification methodologies VMM/OVM
Random test generation, Test planning and Test writing especially for processor verification
Exposure to tools like: VCS/NCSim, Debussy
Scripting skills

· Exposure to complete SOC Tape-out flow including Silicon debug



SDE / MTS



Develop and execute functional verification plans. Design and implement verification components used to verify correctness of hardware designs, such as checkers, stimulus/irritation generators, simulation infrastructure, and coverage terms. Develop and apply directed and pseudo-random stimulus to appropriately exercise the design. Debug failing tests to root cause. Work with other design engineers to incorporate and verify fixes.



Prove design under test will be deterministic on the ATE tester. Qualify and deliver full-chip stimulus for use in Silicon ATE for product characterization and test. Contribute to the continuous improvement of verification environment and methodology.



Requirements:



· Candidate must have a Master's degree (EE/CompE/CS); or Bachelor's degree (EE/CompE/CS) with at least 3 years relevant experience. Additional experience is a plus.Experience in UNIX environment.

· Software experience in Verilog, SystemVerilog, Perl, assembly and/or C/C++.

· Logic simulation and debugging, including application of industry-standard verification tools (VCS/Verdi).

· Background and interest in SoC validation, pre-silicon and post-silicon.

· Able to work independently, be self motivated and enthusiastic to learn new methodologies, and have excellent communication skills to succeed in a multi-site international work environment.

· ATE, JTAG, and DFT experience is a plus.

SDE / MTS





Preferred Education and experience: The Candidate should have a Master's with 4+ years of experience or Bachelor of Engineering with 6+ years of experience in electronics or Computer engineering. Experience in large ASIC or processor design/verification, SoC/Processor architecture and micro architecture, C/C++ programming language, scripting languages, and simulation and debug tools is a must. Candidate should have experience in SoC Verification a large ASIC/Processor, design and debug using Verilog/system Verilog (or equivalent HVL). Processor verification experience is an added advantage.


Primary Purpose: Primary job function is to work with verification technical lead of area/feature at full chip level and meet grade level expectations


Key Job Functions: Perform IP/SOC integration, qualify the models with high coverage test suite and release to verification team. Play a key role in verification environment development (detailed test plans, checkers, irritators, models, stimuli) and debug and root cause failures. Good team work to ensure timely and quality deliverables. Meet grade level expectations (technical leadership, innovation, supervision requirement, ownership, problem solving, mentoring), key being ability to operate independently with minimal supervision.



SDE / MTS



Soc-DFT Verification



Preferred Education and experience: The Candidate should have a Master's with 4+ years of experience or Bachelor of Engineering with 5+ years of experience in electronics and communication or Computer engineering. Experience in large ASIC or processor design/verification, C/C++ programming language, scripting languages, and simulation and debug tools is a must. Candidate should have experience in front-end verification of Soc-DFT features which includes MBIST, LBIST, Boundary Scan, Scan-dump features. Processor verification experience is desired.

Primary Purpose: Primary job function is verification of area/feature mentioned above at the full chip level and meet grade level expectations

Key Job Functions: Own and verify an area/feature at full chip level. Play a key role in verification environment development (detailed test plans, checkers, models, stimuli) and debug and root cause failures. Good team work to ensure timely and quality deliverables. Meet grade level expectations (technical leadership, innovation, supervision requirement, ownership, problem solving, mentoring). Expected to resolve issues and come up with innovative verification approaches and solutions



GSE

Physical Design Manager



The Physical Design Manager will be responsible for the planning and execution of all physical design activities for a given ASIC products. She/he will be responsible to manage a group of 6 to 12 engineers on Physical Design (place and route) duties both on block, as well as global top-level, which includes: top-level floor planning, placement, scan-reordering, clock tree synthesis, in place optimization, routing, timing analysis/closure and ECO tasks (timing, functional, noise based ECOs), design rule checks (DRC), and Logical vs. Schematic (LVS) checks.

The candidate will be responsible for:

· Resource management, hiring and training.

· Provide technical direction, mentoring, skill development

· Forward thinker to improve process and innovation

· Interface with other ASIC Managers/Directors to define schedules, resource requirements etc.,

· Provide leadership and direction in crisis

· Interface with front-end ASIC teams to resolve issues and problems

· Responsible for execution of program. Multiple projects on the go.



In addition, strong communication skills and an ability to work in large groups are essential to being successful. Some insight to multi-site project development will be an asset.



Requirements



Minimum 10+ years of ASIC physical design experience.

Leadership and Mentoring skills a must.

Management experience an asset.

Strong Back ground of ASIC Physical Design: Floor planning, P&R extraction, IR Drop Analysis, timing and Signal Integrity closure.

Hands on experience and detailed knowledge in Cadence or Synopsys or Magma ASIC Physical Design Tools

Scripting Language with PERL, TCL, AWK, shell scripting a very big asset.

Familiar with Physical Verification is also desirable.





SDE



Exp: : 5 -10 year




Key Responsibilities



This is a full time position in our Hyderabad office. This position requires interface with large front-end design teams in US, Canada, Shanghai and India, mentoring new hires and owing physical design of 2 to 3 subchips(blocks), or partitioning, IR drop analysis, fullchip timing etc.,



The Senior Engineer will be responsible for execution of Full chip floor planning and block level physical design activities for a given ASIC product, which includes: floor planning, placement, scan-reordering, clock tree synthesis, in place optimization, routing, timing analysis/closure and ECO tasks (timing, functional, noise based ECOs), design rule checks (DRC), and Layout vs. Schematic (LVS) checks. In addition to this, He/She will also be participating in Physical design Flow development/upgrade by continuously working with the internal design teams and CAD vendors.



In addition, following is desirable:

Ø Understanding Verilog HDL

Ø Understanding Deep Submicron effects such as 65nm and below

Ø Understanding OCV, DFM, DFY

Ø Good timing concepts

Ø Displaying motivation, leadership skills and working in teams

Ø Effective written and oral communication skills in English





Job Requirements:



Ø Minimum 4 year of ASIC physical design experience.

Ø Reasonable Back ground of ASIC Physical Design: Floor planning, Clock Tree Synthesis, P&R extraction, IR Drop Analysis, timing and Signal Integrity closure.

Ø Hands on experience and reasonable knowledge in Cadence and Synopsys Physical Implementation Tools

Ø Should have participated in a minimum of 2 to 3 tapeouts.

Ø Knowledge with Scripting Language with PERL, TCL, AWK, shell scripting

Ø Familiar with Physical Verification will be a plus.


Should have participated in a minimum of 3-4 fullchip tapeouts.



CAD



SMTS



Skills: Have worked on the complete design flow, developed methodologies, flows, tools in his past background. Strong in Timing, Noise/Signal Integrity, Physical Verification. Have expertise in commercial EDA vendor tools from Synopsys, Mentor, Cadence, Apache etc.

Programming: PERL, Tcl. C++



12+ years of experience

MTS



Skills: Strong programming skills, worked on some parts of the design flow, developed methodology/flows in his past work. Very good understanding in one of these: Physical Verification, Place&Route. Should have used commercial EDA tools from Mentor, Synopsys.

Years of experience: B.Tech + 5-8 years; M-Tech + 3-4 years (M.Tech from IITs, IISc)

Check www.amd.com

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1 comments

  1. Anonymous // December 11, 2010 at 11:57 AM  

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